1. Field of the Invention
This invention relates to programmable logic arrays and specifically to a particular macrocell architecture for a programmable logic array.
2. Description of the Related Art
Programmable logic arrays, for instance programmable logic devices (PLDs), typically include a plurality of function blocks interconnected by an interconnect matrix. Each function block includes a programmable array of AND gates as well as a plurality of macrocells which receive product terms from the programmable array. The macrocells are essentially identical prior to programming. An illustrative function block includes 18 macrocells receiving 90 product terms from the programmable array, i.e. five product terms per macrocell.
FIG. 1A shows a generic AND array 10 driving a set of sense amplifiers 14 which in turn provides five product terms 1-5 for a macrocell 16. Note that only a portion of macrocell 16 is shown; each macrocell also includes a flip-flop, output buffer, and other elements which are not shown but are well known to those in the art. See e.g. The Programmable Gate Array Data Book, pp. 3-5 to 3-12, Xilinx, 1994, incorporated by reference herein. In one embodiment, product terms 1-5 are inverted by inverters I1-I5, respectively.
Product terms 1-4 of the macrocell are provided to a conventional NOR gate 20 (shown at the transistor level including transistors Q1-Q4 and Q6), wherein the output signal of NOR gate 20 is provided to the D input terminal of the macrocell flip-flop (not shown) via line D. The product term on line 5 drives the asynchronous active-high programmable reset (or set) input signal to the macrocell flip-flop. Thus, of the five product terms in the prior art, only one product term, i.e. product term 5, sets or resets the flip-flop. A gate level version of NOR gate 20 is shown in FIG. 1B. Therefore, only four product terms are used for the logic function of driving the D (data) input to the macrocell flip-flop. A more flexible structure in terms of use of the product terms would be desirable, but is not available in the prior art.